In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, creating an integrated circuit (IC).
To reduce sheet resistance, a metal oxide semiconductor (MOS) transistor employs a polycide gate. The polycide gate comprises metal silicide, such as tungsten silicide (WSi.sub.x) over heavily doped polysilicon (poly). Typically, the poly is doped with phosphorus (P). The poly should contain a high dopant concentration to lower its sheet resistance.
However, metal silicide over heavily doped poly exhibits stoichiometric control problems, which are expressed in the form of a metallic-rich interface. A metallic-rich interface is undesirable since it is not resistant to subsequent thermal processes. As a result, the interface gets oxidized. Oxidation causes surface roughness and, in some cases, delamination of the silicide film. Conventionally, the adverse effects of the metallic rich interface are avoided by providing an intrinsic (undoped) layer of poly between the heavily doped poly and the metal silicide. The addition of the undoped poly layer increases the height of the gate stack, increasing the aspect ratio of the gate stack. Decreasing the groundrules further increases the aspect ratio, resulting in process problems. Further, the addition of the undoped poly layer also increases the gate resistance, which decreases device performance. Another technique that avoids a metal-rich interface is to lower the dopant concentration of the poly. Typically, the P concentration of the poly layer should be kept below 10.sup.20 atoms/cm.sup.3. Such technique also undesirably increases the gate resistance.
From the above description, it is desirable to provide a reliable polycide gate with reduced sheet resistance.